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AMIS-492x0
Fieldbus MAU
1.0 Introduction
1.1 Overview AMIS-492x0 Fieldbus MAU (media access unit) is a transceiver chip for low speed FOUNDATION Fieldbus(R) and Profibus(R) PA devices. The AMIS-49200 was originally designed to be a near pin-for-pin replacement of the Yokogawa SAA22Q MAU. "Near pinfor-pin" means that associated component values may change, but no board changes are required. A micro-leadframe package option (NQFP) is also available, the AMIS-49250. 1.2 Definitions, Acronyms and Abbreviations IC ESD FF LQFP Manchester MAU MDS NQFP SAA22Q - Integrated circuit - Electrostatic discharge - FOUNDATION Fieldbus - Low profile quad flat pack - Communications encoding scheme implemented in FOUNDATION Fieldbus - Medium attachment unit - Medium dependent sub-layer - "Near chip-scale" quad flat pack - Name of Yokogawa's MAU IC
1.3 References * Fieldbus Medium Attachment Unit (MAU) Chip, SAA22Q, Yokogawa Electric Corporation, June 12, 1998, Document No.: SS-96-01 (Rev.3). * Fieldbus Standard for Use in Industrial Control Systems Part 2: Physical Layer Specification and Service Definition, Amendment to Clause 22 ISA/SP50 -1996-544B, dS50.02, Part 2, Draft Standard. * Profibus PA specifications EN 50170 (formerly DIN 19245) covers all of Profibus and includes PA (31.25 kbps Intrinsically Safe Physical Layer), references IEC 61158-2.
(c)2008 SCILLC. All rights reserved. June 2008 - Rev. 6
Publication Order Number: 492x0/D
AMIS-492x0
2.0 AMIS-492x0 Fieldbus MAU Description
2.1 Features AMIS-492x0 Fieldbus MAU is a transceiver IC for low speed FOUNDATION Fieldbus and Profibus PA devices. It incorporates the following features: * All node power can be supplied by the bus, via the AMIS-492x0 * Current consumption 500uA (typ) * VCC voltage: 6.2V to 4.75V * VDD voltage: 5.5V to 2.7V * Compatible to IEC 1158-2 and ISA 50.02 * Shunt regulator * Voltage reference (internal only) * Series regulator * Band-pass filter * Slew rate control * Segment current control * Low voltage detection * Carrier detect * Data rate: 31.25kbps voltage mode * Dual voltage supply 3-6.2V * 44-pin LQFP/NQFP package
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AMIS-492x0
2.2 Block Diagram
33
31 VSS
FLTOUT
30
FLT
Receive Block
35 RXS Zero-Cross Detector
HPF Bandpass Filter SIGIN LPF
28 27 29
34 32
RXA CCD
Carrier Detector
Transmit Block
26 38 36 37 1 41 42 43 39 40 44 18
VDD
MDS_CTRL POL TXE TXS VSS VSS VSS VSS Current Driver MDS Interface Tri-Level Modulator & Slew Control
VDRV CRT VSS VSS CCINP CCINM CCOUT
21 19 20 22 23 24 25
VSS VSS
VCC VCC
Power Supply Block
VCC VCC
VCC
Vmid Reference
Vmid
Vmid
3
Bias Circuitry
Bandgap
Vref
Vref
2
17
VCC
16 13
VO SRSET VSS 11 Series Regulator Low Voltage Detectors SRSETIN 12 Shunt Regulator
SHUNT
8
SRTR SRAO 15 14
N_PFail2 5
N_PFail1 4
SHSETIN SHSET SGND 6 7 9
Figure 1: AMIS-492x0 Fieldbus MAU Block Diagram
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VSS 10
AMIS-492x0
2.3 Package Information The IC is packaged as shown below.
Figure 2: AMIS-49200 Package Dimensions (44-pin LQFP)
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AMIS-492x0
Figure 3: AMIS-49250 Package Dimensions (44-pin NQFP)
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AMIS-492x0
Table 1: Pin Numbers and Signal Description Signal Name Pin No. I/O (Note 1) VSS VREF VMID N_PFAIL1 N_PFAIL2 SHSETIN SHSET SHUNT VSS/ SGND VSS VSS SRSETIN SRSET SRAO SRTR VO VDD VCC CRT VSS VDRV VSS CCINP CCINM CCOUT MDS_CTRL SIGIN HPF LPF FLT FLTOUT CCD VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 Ground AO AO AI/O AI/O AI AO AI Ground Ground Ground AI AO AO AI AO Digital supply Analog supply AI/O Ground AO Ground AI AI AO AI AI AI AI AI AO AO Ground
Description Connect to ground Internal bandgap voltage (1.18V) 2V bias voltage for AC signals Power fail alarm at VCC input. This pin is an open-drain output of negative logic. Power fail alarm at VDD input. This pin is an open-drain output of negative logic. Feedback (non-inverting) input for the shunt regulator Divided voltage of VCC input. Feeding this voltage to SHSETIN pin results in 5V voltage at VCC. Control pin of the shunt regulator. Its sink current (25mA max) is controlled so that the voltage at SHSETIN is equal to VREF (1.18V). The current absorbed by SHUNT pin (25mA max) is fed to this pin, which must be connected to the ground level Ground Ground Feedback (inverting) input for the series regulator. The series regulator controls its output (SRAO) to make this input voltage is equal to VREF (1.18V). Divided voltage of VO output. Feeding this voltage into SRSETIN pin results in 3V at VO pin. Output pin of an operational amplifier for the series regulator Gate of a PMOS transistor for the series regulator Output pin of the series regulator (20mA max) Supply voltage input for digital block Analog supply voltage Current integration to limit output slew rate Ground Output of an operational amplifier for slew rate control. This signal can be fed to current driver. Ground Non-inverting input of an operational amplifier for transmission current driver Inverting input of an operational amplifier for transmission current driver Output of an operational amplifier for transmission current driver For POL = VDD MDS_CTRL should = VSS For POL = VSS MDS_CTRL can be tied to VDD or used as a not reset to control when transmit communications will be enabled Input pin of the band-pass filter. This pin is connected to VMID bias level with 270K resistor. Feedback signal of high-pass filter. This pin is connected to the output of an op-amp for high pass filter with 75K resistor. Non-inverting input of an operational amplifier for the low-pass filter Input pin of low-pass filter for feedback. This pin is connected to the output of the high-pass filter through 20k and the non-inverting input of the low-pass filter through 54k resisters. Output of the operational amplifier for the low-pass filter. This signal is internally connected to non-inverting input to form a voltage-follower. Current integration (for carrier detect circuit) Ground
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AMIS-492x0
Table 1: Pin Numbers and Signal Description (Continued) Signal Name Pin No. I/O(Note 1) Description RXA RXS TXE TXS POL VSS VSS VSS VSS VSS VCC
Note: 1. AI = Analog Input, AO = Analog Output, AI/O = Analog Input/Output, DIS = CMOS Digital Input (Schmitt Trigger), DO = CMOS Digital Output.
34 35 36 37 38 39 40 41 42 43 44
DO DO DIS DIS DIS Ground Ground Ground Ground Ground Analog supply
MDS-MAU interface signal for received signal activity. This pin is a push-pull output. MDS-MAU interface signal for received signal. This pin is a push-pull output. MDS-MAU interface signal for enable signal transmission (Schmitt Trigger input) MDS-MAU interface signal for signal to be transmitted (Schmitt Trigger input) Selects polarity of TxE input. When this pin is connected to GND, TxE is active high. When this pin is connected to VDD, TxE is active low. Ground Ground Connect to ground Connect to ground Connect to ground Analog supply voltage
3.0 Electrical Characteristics
3.1 Operating Conditions
o Unless otherwise noted, all block and sub-block specifications apply over the operating temperature (-40 to 85 C).
Table 2: Absolute Maximum Ratings Parameter Analog block supply voltage Digital block supply voltage Digital input pin voltage Digital output pin voltage Input pin current Output pin current ESD, Human Body Model ESD, Machine Model ESD, Charged Device Model Storage temperature
Symbol VCC VDD VIN VOUT IIN IOUT
Min. -0.3 -0.3 -0.3 -0.3 -
TStorage
-55
Max. 6.5 6.0 VDD + 0.3 VDD + 0.3 5 30 2,250 250 1,000 125
Units V V V V mA mA V V V C
Conditions
(TxS, TxE and POL pins) (RxS and RxA pins) Not for shunt pin For shunt, SGND and VO
Table 3: Normal Operating Conditions Parameter Symbol Analog supply voltage VCC Digital supply voltage VDD Storage temperature TOperating Current consumption ICC
Min. 4.75 2.7 -40
Typ. 5 3 500
Max. 6.2 VCC - 1.1V 85 800
Units V V C A
Conditions Supply voltages are configurable, or can be supplied from off-chip 25C, SHUNT current = 1mA, No current from series regulator
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AMIS-492x0
Table 4: CMOS Input Specifications Parameter Input high voltage Input low voltage Input high current Input low current Schmitt negative threshold Schmitt positive threshold Schmitt hysteresis Symbol VIH VIL IIH IIL VtVt+ Vh 1 0.2*VDD 0.8*VDD Min. 0.7*VDD 0 Max. VDD 0.3*VDD 1 -1 Units V V A A V V V
3.2 Power Supply Blocks
Table 5: Regulator Specifications Parameter Shunt Regulator Output voltage Sink current Load capacitance Load regulation Temperature coefficient Series Regulator Input voltage Output voltage
Symbol VCC ISH CSH TCVcc VCC VO
Min. 4.85 4.75 0.001 5 0
Typ. 5.0
Max. 5.15 6.2 25 4 200 6.2
Units V V mA F % ppm/C V V V mA F % ppm/C % Vref V A A
Conditions Preset, ISH = 1 to 5mA External setting Internal pass transistor N-ch and pad ISH = 1 to 25mA No load capacitance Internally tied to VCC pin Preset, ISR = 0 External setting and N-JFET Internal pass transistor P-ch and pad For stability use Cap w/ ESR ISR = 0 to 20mA
1.6
4.75 2.91 2.85 3.0
3.09 3.5 20 4
Output current ISR Load capacitance CSR 5 Load regulation 0 2 Temperature coefficient TCVo 200 Low Voltage Detectors (applies to N_PFail1 and N_PFail2) Threshold VTH9 85 90 Hysteresis Output sink current Output leakage current VHYS5 IOL IL .012 30 .025
95 .038 135 1
SxSETIN > VTH9 (output: L SxSETIN < (VTH9 - VHYS5) (output: H L) VOL= 0.4V (open drain) VOH = 5V
H)
Table 6: Voltage Reference Specifications Parameter Symbol Bandgap Voltage Reference Output voltage tolerance VREF Temperature drift Hysteresis
(1)
Min. 1.157 4.75 1.95 -30 0.01
Typ. 1.185 50 100 5 2.0 0.1
Max. 1.205 6.2 0 2.05 100 1 200
Units V ppm/C V V A V A F ppm/C
Conditions Equates to: +/- 2 percent Note 1 No load during operation
VREFHYS VCCREF IREFOUT VMID IMID CMID TCMID
Supply voltage Load current VMID voltage reference Output voltage Output current Load capacitance Temperature coefficient
Notes: 1.
DVC6000F uses 1uF
Hysteresis is defined as the change in the 25C reading after 85C to 25C cycle and -40C to 25C cycle.
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AMIS-492x0
3.3 Transmitter Blocks
Table 7: MDS-MAU Interface Parameter MDS-MAU Interface POL input pin TxE input pin TxS input pin
Symbol POL TxE TxS
Min.
Typ.
Max.
Units V
Conditions
See Schmitt Trigger input specs
V V
Note: The associated MDS chip must handle the jabber detect function.
Table 8: Tri-level Modulator Parameter Symbol Tri-level Modulator and Slew Control Output voltage VO Load current IO Output for silence
(1)
Min. VMID -35 VMID+0.485 VS+0.380 VS-0.420 -0.02
Typ.
Max. 3.02 +120
Units V A V V V V sec
Conditions (Output is at VDRV) |V| 10mV TXE disabled TXE active TXE active Note 2 (CRT= 22pF)
VS
(1)
VMID+0.500 VS+0.400 VS-0.400
VMID+0.515 VS+0.420 VS-0.380 0.02
Output for high level Output for low level
VH VL VHL tf, tr
(1)
Asymmetry of VH and VL Rise and fall times
Notes: 1. 2.
(2)
4.7
Nominal values are: VS = 2.5V, VH = 2.9V and VL = 2.1V. By adding an external capacitor between the CRT pin and ground, slew rate at VDRV output can be controlled. The controlling equation is tf or tr = 2us + (0.123us/pF * CRT). CRT is nominally 22pF, yielding tf = tr =4.7us. The constant comes from an internal capacitor. The hot side of the capacitor and the CRT pin should have a guard pattern around them to avoid unnecessary interference.
Table 9: Current Control Amplifier Parameter Current Control Amplifier Input common mode voltage range Output voltage swing Load current Input offset voltage Slew rate Gain bandwidth product Phase margin
Symbol VCM VO Io VOS SR GBW PM
Min. 0 1 -2300 -3
Typ.
Max. VCC - 1 VCC - 0.5 100 +3
Units V V A mV V/s MHz Deg
Conditions (Output is at CCOUT)
0.54 1.15 66
CL= 10pf RL= 200k
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AMIS-492x0
3.4 Receiver Block
Table 10: Receiver Sub-blocks Parameter Band Pass Filter Input voltage Output voltage swing Output slew rate Input offset voltage
Symbol VBP FLTOUT SR VOS RF1
Min. 1 1
Typ.
Max. 4 4
Units V V V/s
Conditions SIGIN pin to GND
0.6 5 60 216 16 43 40 -60 VDD-0.6 0.3 50 50 0.3 0.3 VMID+0.025 VMID VDD-0.6 0.3 50 50 0.3 0.3 VMID+0.040 VMID VMID+0.058 VMID 75 270 20 54 50 -50 90 324 24 65 60 -40
mV k k k k mV mV V V A A s s V V V V A A s s
Filter resistors
(1)
RF2 RF3 RF4
Carrier Detector Threshold voltage Output high voltage Output low voltage Output high current Output low current Output rising time Output leak current Zero-cross Detector Threshold voltage Output high voltage Output low voltage Output high current Output low current Output rising time Output leak current
Note: 1. The band pass filter is made up of a two pole high pass filter in series with a two pole low pass filter. The filter consists of four resistors internal to AMIS-492x0, and four external capacitors. The active part of each filter is an amplifier connected in a follower configuration.
VTH+ VTHVOH VOL IOH IOL tR tF VTH+ VTHVOH VOL IOH IOL tR tF
Relative to VMID IOH = 0mA IOL = 0mA VDD-VO 0.6V VO 0.6V CL = 10pF CL = 10pF No carrier Carrier active IOH = 0mA IOL = 0mA VDD-VO 0.6V VO 0.6V CL = 10pF CL = 10pF
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AMIS-492x0
4.0 Theory of Operation
4.1 Overview The AMIS-492x0 incorporates two different power supply circuits. Both derive their power from the bus. Using the internal configuration, the shunt regulator is set for 5V and the series regulator is set for 3V. Users can modify either power supply by adding external components. The AMIS-492x0 Fieldbus can also monitor these power supply voltages and generate power-fail signals if they fall below a specified value. Please refer to the AMIS-492x0 Fieldbus MAU Reference Design Application Note for ways to adjust the shunt and series voltage regulators. The AMIS-492x0 Fieldbus MAU transmits a Manchester-encoded signal provided from a standard MDS-MAU interface. The output driver makes it possible to design various signal circuits, which depend on the power requirements of your device. The slew rate of the signal can be controlled to minimize unnecessary radiation as specified in IEC/ISA standards. The AMIS-492x0 Fieldbus MAU has a built-in band pass filter which makes it easy to design your own receiver. The receive block operates on a Manchester-encoded signal. It decodes the signal and verifies proper amplitude with a zero-cross and carrier detect circuit, respectively. Detected signals are then passed on to a controller with the standard MDS-MAU interface. 4.2 Power Supply Block The power supply block contains four sub-blocks: 1. 2. 3. 4. A shunt regulator - for establishing a supply voltage of VCC (typ. = 5V) used by the analog circuitry A series regulator - for establishing a supply voltage of VDD (typ. = 3V) used for digital circuitry Two low voltage detectors - for monitoring the two supply voltages A bandgap voltage reference - which is used internally for generating a bias level for AC signals
4.2.1. Shunt Regulator The shunt regulator controls its sink current to the SHUNT pin so that the voltage applied to the SHSETIN pin is equal to VREF. The VCC input is divided by an internal network to provide a voltage equal to Vref at the SHSET pin. If SHSET and SHSETIN pins are tied together, and VCC and SHUNT pins are connected to a power source of high impedance (e.g., current mirror circuit of signal driver), the shunt regulator provides 5V power to itself and external circuits. A capacitor of 5F or larger capacity is necessary to stabilize this regulator. Figure 13 shows C10 (22F) connected to Pin 8 to accomplish stabilization. It is possible to increase the VCC voltage up to 6.2V by dividing VCC with an external network to supply the appropriate voltage to SHSETIN pin. In this case, SHSET pin must be kept open. The output voltage is determined by the following equation: VCC = VREF x (1 + R1 / R2)
Shunt Regulator (Internal Configuration )
VCC
System VCC
Shunt Regulator (External Configuration )
VCC
System VCC
18
3.25Rsh 16Meg VREF Rsh A6 Cfb 50pF 25mA (Max) SHUNT 3.25Rsh 16Meg VREF Rsh A6 Cfb 50pF 25mA (Max)
18
R1 SHUNT
8
8
R2
7
SHSET
6
SHSETIN
9
SGND
7
N/C
SHSET
6
SHSETIN
9
SGND
Figure 4: Shunt Regulator
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AMIS-492x0
The SHUNT pin is normally connected to VCC. It is possible to insert a resister between VCC and SHUNT to measure the shunt current. Its value should be small enough to keep VDS (voltage between SHUNT pin and SGND pin) larger than 2.5V (i.e., resistor must be less than 100.). Since the internal transistor can sink as much as 25mA, no additional circuit is necessary in most cases. Note that the drain current must not exceed 25mA because no protection is implemented for the internal transistor. If you do not need the shunt regulator, you should connect SHUNT and SHSETIN pins to GND and open SHSET pin. Then VCC must be supplied from another source. 4.2.2. Series Regulator The series regulator produces a regulated voltage at the VO pin from VCC. If you connect SRAO and SRTR pins together, the internal amplifier will regulate the input voltage at SRSETIN pin to equal VREF. An internal feedback signal is generated to produce a voltage equal to VREF at pin SRSET. If you connect SRSET and SRSETIN pins, the series regulator supplies 3V at pin VO. A capacitor (CD in Figure 5) of 5F or larger capacity is necessary to stabilize this regulator. The capacitor is expected to have an ESR resistor for the circuit to be stable. If the capacitor is low, a series resistor with the cap load will help stabilize the circuit).
Series Regulator (Internal Configuration)
May Supply VDD VO Cfb1 20mA (Max) Cc2 20pF 1.54Rsr A7 VREF 40pF VCC May Supply VDD VO
Series Regulator (External Configuration)
Cfb1 20mA (Max) Cc2 20pF 1.54Rsr A7 VREF 40pF VCC
16
CD SRSET
16
CD R4 SRSET N/C
13
Rsr R5
13
Rsr
SRTR
15
14
SRAO
12
SRSETIN
SRTR
15
14
SRAO
12
SRSETIN
Figure 5: Series Regulator
The supply current must not exceed 20mA because no current limiting is applied to the internal transistor. You can increase VO voltage up to 3.5V by dividing VO with an external network to supply the appropriate voltage to pin SRSETIN. In this case, pin SRSET must be kept open. The drain-source voltage of the internal transistor must be larger or equal to 2V. If this condition is not satisfied, you may need an external P-channel JFET to create the desired low voltage-drop regulator. The output voltage is determined by the following equation. VO = VREF x (1 + R4/R5) 4.2.3. Low Voltage Detectors Low voltage detectors are included to monitor supply voltages and generate "power fail" signals. The low voltage alarms are detected by sensing the voltage on pins SHSETIN and SRSETIN. These pins also provide feedback for the shunt and series regulators. If the voltage on the SHSETIN pin is lower than the threshold, VTH9 (90 percent VREF), N_PFAIL1 goes low. Typically SHSETIN monitors the analog rail voltage VCC. If the voltage on the SRSETIN pin is lower than the threshold, VTH9, N_PFAIL2 goes low. Typically SRSETIN monitors the digital rail voltage VDD. Both outputs are open drain, so a resistor will be required. If you do not use one of these pins, it should be connected to GND. You can also add capacitors to delay these signals. In this case, sink current must not exceed the maximum value. If you do not wish to use one of the low voltage detectors its corresponding output pin should be connected to GND.
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AMIS-492x0
Low Voltage Detectors
VDD R1
VCC2 0.9*VREF C3 SHSETIN
N_PFail1
4
C1 VDD R2
VCC2 0.9*VREF C4 SRSETIN
N_PFail2
5
C2
Figure 6: Low Voltage Detectors
If you do not use one of the regulators, the corresponding alarm signal can potentially be used to monitor another signal. For example, if the series regulator is not used, SRAO should be left open, SRTR tied to VCC, VO grounded and SRSET left open. Then SRSETIN can be the input for monitoring another voltage signal with N_PFAIL2. 4.2.4. Voltage Reference The voltage reference circuitry generates two voltage signals, VREF and VMID. VREF comes from a bandgap circuit and is used as the reference voltage for all circuits in the AMIS-492x0 Fieldbus MAU. The typical value for VREF is 1.185V. See Figure 7. An operational amplifier is regulating VMID to provide a bias (common) level for the AC signals. Its typical voltage is 2V. A capacitor larger than 0.01F is necessary on VMID to remove high-frequency ripple.
Figure 7: Bandgap and VMID Voltage Reference
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AMIS-492x0
4.3 Transmit Block The transmit block contains four sub-blocks: 1. 2. 3. 4. MDS-interface - decodes input signals to generate internal control signals. Tri-level modulator - generates current signals used as inputs to the slew-rate controller. Slew rate controller - converts current to three distinct VDRV voltage levels (VS, VH, VL). Current drive amplifier - op amp designed to drive current drivers for 31.25kbps voltage-mode medium.
4.3.1. MDS-interface The MDS-interface decodes input signals to generate internal control signals. The POL pin is used to select the polarity of TxE (transmit enable). The TxE and TxS (transmit signal) are the MDS-MAU interface signals. These three signals are CMOS logic signals powered by the VDD supply voltage. When POL is connected to GND, TxE is assumed to be active high (positive logic). Likewise, if POL is connected to VDD, TxE is assumed to be active low (negative logic). See Table 1 on page 7, Table 11, and Figure 8 to see how MDS_CTRL Pin 26 can be used to control MDS interface operation. Table 11 shows the resulting VDRV output for the various combinations of interface signals.
Table 11: MDS-interface Logic POL TxE TxS Low Low High Low Low High High Low Low High High Low High High VDRV VS VH VL VH VL VS
Figure 8: MDS Interface
4.3.2. Tri-level Modulator The tri-level modulator switches current signals into a summing node. The slew rate controller converts the current to a voltage signal, VDRV. The DC level of silence (VS) is nominally 2.5V. Transmission high (VH ) is nominally 2.9V and transmission low (VL) is nominally 2.1V, yielding an amplitude of 0.8V.
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AMIS-492x0
Tri-Level Modulator & Slew Control
N_VL N_Vs
Active Low
Active Low
4R 80K
4R 80K
R 20K VCC VDRV
1.2K
20R 400K
A3 VMID
21 19
1.2K
CRT
1.2K
Figure 9: Tri-level Modulator
4.3.3. Slew Rate Controller Amplifier (A3), shown in the above figure, controls the slew rate. The amplifier converts the current signals from the tri-level modulator to a voltage signal, VDRV. It controls its slew rate with a capacitor (CRT) connected to the CRT pin. The waveform at the VDRV pin is symmetric and the fall/rise times are determined by the following equation: tF, tR = 2.0[s] + 0.12 [s/pF] x CRT The constant part comes from the internal capacitor (not shown). It is recommended to make a guard pattern on your circuit board around the CRT pin and the hot side of CRT to avoid unnecessary interference. 4.3.4. Current Drive Amplifier The drive amplifier is an operational amplifier optimized to drive current drivers for 31.25kbps voltage-mode medium. Its input and output signals are exposed to allow flexible design of the external driver. Note that this amplifier cannot directly sink the necessary current from the medium. In the following drive circuit the current (IBUS) through the current-detect resister (RF) is determined by the following equation. I bus = [ R3 Vmid (R12 + R11 ) ] - [ Vdrv (R2 R11 + R3 R11 ) ] - [ RF ( R2 R12 + R3 R12 ) ] A diode and/or a resistor connected to the emitter are necessary to shift the DC level of CCOUT and to suppress the loop gain. The resistance value depends on your design (overall gain and emitter current).
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AMIS-492x0
Figure 10: Current Control Circuit
4.4 Receive Block The receive block contains three sub-blocks, which are internally connected: 1. 2. 3. A band pass filter - to filter the desired incoming communication signal. Carrier detector - generates the RxA signal by detecting the signal amplitude. Zero-cross detector generates the RxS signal by detecting the high/low transitions of the Manchester code.
4.4.1. Band Pass Filter The band pass filter is a series connection of a high-pass and a low-pass filters each having two poles. Each filter is comprised of a voltage follower and on chip resisters, so only four external capacitors are necessary. The following figure shows an internal circuit and the connection of external capacitors. Cut-off frequency, fL, of the high-pass filter is determined by C1 and C2 while cut-off frequency, fH, of the low-pass filter is determined by C3 and C4.
fL =
1 2
1 R F1 *R F 2 *C1 *C 2
QL =
1 2
R F2 R F1
=0.95 =0.95 The values in the following figure are
fH =
1 2
1 R F 3 *R F 4 *C 3 *C 4
Q L = 0.44 *
C3 C4
The possible ranges of fL and fH are 1kHz ~ 10kHz and 10kHz ~ 100kHz, respectively. recommended to obtain 1kHz and 47.6kHz cut-off frequencies.
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AMIS-492x0
C3=220pf FLTOUT
Bandpass Filter
31
To Detectors
30 FLT
RF1 75K HPF
28
VCC VCC A2 RF4 54K RF3 20K A1 SIGIN C2 C1 Signal Input 1000pf
27
RF2 270K Vmid 1000pf
29
C4=47pf
Figure 11: Band Pass Filter
4.4.2. Receive Signal Detection The carrier detector generates the receive activity (RxA) signal by detecting the input signal amplitude. Minimum amplitude is 100mVpp (TYP). A delay, determined by the capacitor connected between the CCD pin and GND, is added to avoid detection of transient noise. The recommended value of CCD is 100pF. The output can drive a CMOS input of VDD supply voltage. The zero-cross detector generates the receive signal (RxS) with minimum phase error (jitter) by detecting the transition between high and low levels of the incoming Manchester code. Hysteresis of +40mV (TYP) is applied to avoid unnecessary switching by noise. Once the carrier-detect goes active the hysteresis is removed and the switching point threshold is set to Vmid. The output can drive a CMOS input of VDD supply voltage.
Zero-Cross Detector
VDD Level Convert VCC C1
RXS
35
ZC Tript Pt
Vtrip = Vmid Vhyst = + 40mV
Vmid R (1Meg) RxSig C (60pF) VHi50 = Vmid + 50mV VLo50 = Vmid - 50mV Filtered received signal from Bandpass Filter
Carrier Detector
VCC RXA VDD Level Convert CD_Output VCC VLo50 C2 VCC C2 VHi50
34
CCD
32
Figure 12: Receive Signal Detectors
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AMIS-492x0
5.0 AMIS-49200 as Replacement for Yokogawa SAA22Q
The AMIS-49200 is a near pin-for-pin compatible replacement for the Yokogawa SAA22Q Fieldbus MAU. There are some differences between the two chips both in the internal operation, the required external connections and the value (or existence) of some of the external components. These differences are small and those who used the SAA22Q would most likely be able to use the AMIS-49200 in designs with only some component value changes. 5.1 Functional Differences Between the SAA22Q and the AMIS-492x0 5.1.1. Jabber Inhibit The AMIS-492x0 does not implement the Jabber Inhibit function in the SAA22Q. Typically the AMIS-492x0 will be connected with a link controller chip such as the UFC100-F1 from Aniotek/Softing. This link controller has a Jabber Inhibit function so the absence of this function in the AMIS-492x0 should not be a problem. As can be seen in Table 12, MDS_CTRL is only connected to ground if POL is connected to VDD. See Table 1 for a detailed description of the interaction between MDS_CTRL and POL. In Table 12, the SAA22Q recommends that the JAB/ signal (Pin 39) be connected to ground if the signal is not used. On AMIS-492x0, Pin 39 must be connected to ground. 5.1.2. Low Power Mode The low power mode on the SAA22Q allows the user to have a quiescent current draw of less than 10mA yet still communicate at the proper IEC 61158-2 signal levels. Very few, if any, Fieldbus devices are capable of operating at such a low current level so this capability was not included in the AMIS-492x0. The pins affected by this are 41, 42 and 43. If the low power mode is not being used on the SAA22Q, these three pins are grounded. On the AMIS-492x0 it is required that these pins be grounded. 5.2 Pin Differences Between the SAA22Q and the AMIS-492x0
Table 12: Pin Connection Differences Between the SAA22Q and the AMIS-492x0 AMIS-492x0 SAA22Q Pin No. 1 11 22 26 33 39 41 42 43 Signal Name NC NC NC NC NC JAB/ CJB VTX VSL Recommended Connection Ground Ground Ground Ground Ground Ground if not used 1 f cap Ground Ground Signal Name VSS VSS VSS MDS_CTRL VSS VSS VSS VSS VSS Required Connection Ground Ground Ground Ground* Ground Ground Ground Ground Ground
* MDS_CTRL is only connected to ground if POL is connected to VDD. See Table 1 for a detailed description of the interaction between MDS_CTRL and POL.
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AMIS-492x0
5.3 External Circuitry Figure 13 shows the external circuitry required to connect the AMIS-492x0 to an IEC 61158-2 conformant network. This schematic is the circuit that was used to pass the FOUNDATION Fieldbus Physical Layer Conformance test as specified in FOUNDATION Fieldbus specification FF830, Rev 1.5. This circuit is similar but not identical to the circuit recommended by Yokogawa for the SAA22Q.
Figure 13: AMIS-492x0 Reference Circuit Implementation
Table 13 lists the four external component values that need to be changed with using the AMIS-492x0 in a circuit that previously used the SAA22Q.
Table 13: Passive External Component Value Differences Between the SAA22Q and the AMIS-492x0 Component AMIS-492x0 Value SAA22Q Value C1 C3 C4 C8 100pf 100pf 470pf 10nf 150pf 47pf 220pf 1f
C1 connects to signal CCD (Pin 32) and controls the carrier detect assert and drop-out timing. Particular implementations may require that the value of C1 be changed to accommodate received signal level changes introduced by the addition of intrinsic safety components added to the external circuitry. C3 and C4 are part of the receive filter and determine the band pass characteristics of the receive filter. It is unlikely that these would need to be changed. C8 is a noise filter for VMID. It is important that VMID have as little noise as possible as it is used as a reference for many sub-circuits in the AMIS-492x0. C8 must be a large capacitor with maximum of 100nf. C8 recommended value is 1f.
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AMIS-492x0
There is one other minor difference in the recommended external circuitry between the SAA22Q and the AMIS-492x0. Figure 14 shows the start-up circuits recommended for the SAA22Q and the AMIS-492x0. The circuit shown for the AMIS-492x0 is different from that shown for the SAA22Q but either one will work. Both are current sources that turn on when power is applied to the H1 segment terminals so that the AMIS-492x0 can turn on without any turn-on transients on the network.
SAA 22Q Startup Circuit
Loop +
AMIS 49200 Startup Circuit
R5 100 k Loop + R6 1k Q1 D3 5.1 V V Shunt
V Shunt
Figure 14: Recommended Start-up Circuits
5.4 Active Components
Transistors Q1 - Q4 are ordinary small signal transistors. Diodes D1 and D2 are similarly ordinary small signal diodes. Users desiring to replace a SAA22Q with the AMIS-49200 in an existing design should be able to use whatever transistors and diodes were used with the SAA22Q. For new designs, the specified transistors can be used or other devices may be chosen.
5.5 Alternative Designs
Some users of the Yokogawa SAA22Q did not use the exact recommended external circuit for the media interface circuit (see Figure 13). Using the AMIS-492x0 without the Yokogawa recommended external circuit may result in some compatibility problems. There are many alternative designs and it is beyond the scope of this document to identify all possible configurations and their associated design implications. Please refer to the AMIS-492x0 Fieldbus MAU Reference Design Application Note for a recommended, FOUNDATION Fieldbus certifiable board design.
5.6 Verification
All designs using the AMIS-492x0 should re-run the entire physical layer conformance test as defined in FOUNDATION Fieldbus document FF-830, FOUNDATIONTM Specification 31.25 kbit/s Physical Layer Conformance Test. Board layout can alter the behavior of all circuit implementations, even designs that follow the recommended implementation.
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AMIS-492x0
6.0 Ordering Information
Part Number AMIS-49200-XTD AMIS-49200-XTP AMIS-49250-XTD AMIS-49250-XTP Package 44 LQFP 10x10mm (Green/RoHS Compliant) 44 LQFP 10x10mm (Green/RoHS Compliant) 44 NQFP 7x7mm (Green/RoHS Compliant) 44 NQFP 7x7mm (Green/RoHS Compliant) Shipping Configuration Tray Tape & Reel Tray Tape & Reel Temperature Range -40C to 85C -40C to 85C -40C to 85C -40C to 85C
7.0 Appendix (A) - Manchester Encoding
All Fieldbus devices transmit the data onto the media as a Manchester-encoded baseband signal. With Manchester encoding, zeros and ones are represented by transitions that occur in the middle of the bit period (see below). For FOUNDATION Fieldbus H1 and Profibus PA, the nominal bit time is 32sec, with the transition occurring at 16sec. The Manchester encoding rules have been extended to include two additional symbols, non-data plus (N+) and non-data minus (N-). The symbol encoding rules are shown in Figure 15.
32 usec
-T 2 Logical "0"
T 2
-T 2 Logical "1"
T 2
-T 2 "N+"
T 2
-T 2 "N-"
T 2
Figure 15: Manchester Encoding
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AMIS-492x0
8.0 Revision History
Revision 1 2 3 4 5 6 Date April 2006 October 2006 January 2007 February 2008 May 2008 June 2008 Modification Initial release
Update to new AMIS template Update to new ON Semiconductor template; update OPN table Added AMIS-49250
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